1. Technical Field
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device with a structure which increases the operating speed thereof.
2. Description
A semiconductor memory device is a kind of semiconductor device in which information is read from or written to memory cells. In general, a plurality of memory cells for storage of information are included in a semiconductor memory device.
Such a semiconductor memory device, however, has a problem that a plurality of memory cells are widely distributed in the semiconductor memory device and, thus, the shortest access time depends on the position of each memory cell.
For this reason, a semiconductor memory device is set to operate with respect to a rate limiting path, in which a control signal is generated to have the latest timing, in order to input or output information to or from the respective memory cells without error. In general, reading/writing operations performed through the rate limiting path are delayed by 2-3 ns in comparison with those performed through the shortest path.
The rate limiting path is determined mainly in consideration of a delay in transmission of a Row Address Strobe (RAS) control signal, an inconstant transmission speed of a column path, skew of input and output (IO) paths, and so on. Among the above factors, the delay in transmission of a RAS control signal is the most important factor that is considered in determining the rate-limiting path. Skew indicates the distribution of deviation between signals that are generated differently according to the layout of an internal circuit or the number of inverters in a semiconductor memory device.
FIG. 1 is a diagram of IO paths of data, which are determined according to the positions of array blocks, in a general memory cell array. Referring to FIG. 1, a plurality of memory cell array blocks 11 are aligned in a matrix of rows and columns. The memory cell array blocks 11 are located at both sides of a RAS chain 12. Two Column Address Strobe (CAS) chains 13 are arranged in the column direction below the plurality of memory cell array blocks 11.
As shown in FIG. 1, a path 14 of the memory cell array block 11 adjacent to the RAS chain 12 is shorter than a path 15 of the memory cell array block 111 which is further away from the RAS chain 12.
The diagram of FIG. 1 reveals that an increase in the size of a semiconductor memory device results in an increase in skew, i.e., deviation of a signal, between a short path and a long path due to a difference in the layout of an internal circuit.
Accordingly, a semiconductor memory device shown in FIGS. 2A and 2B is suggested to solve the skew. In detail, FIG. 2A is a view of a structure of one conventional semiconductor memory device, and FIG. 2B is a view of a structure of another conventional semiconductor memory device. The semiconductor memory device of FIG. 2A has a structure in which a RAS control signal can be transmitted faster by an increase in the number of RAS chains 12, whereas the semiconductor memory device of FIG. 2B has a structure in which one RAS chain 12 is positioned between two groups of memory cell array blocks and one edge driver 16 is arranged at one side of each of the two groups of memory cell array blocks.
Like the semiconductor memory device of FIG. 2A, the semiconductor memory device of FIG. 2B also has a structure in which an RAS control signal can be transmitted faster. The edge driver 16 receives a control signal from the RAS chain 12 and activates the respective memory cells.
However, although a semiconductor memory device having a structure shown in FIG. 2A or 2B is advantageous in that skew is reduced due to an increase in the speed of transmission of the RAS control signal, the additional RAS chain(s) or the edge drivers take up a large amount of space of the semiconductor memory device.
FIG. 3 is a timing chart illustrating signals that are related to data output from a general semiconductor memory device. In detail, FIG. 3 shows the types of skew that occur in the respective control signals passing through various paths of a memory cell array block 11. Referring to FIG. 3, the bold lines indicate signals passing through the shortest path and the fine lines indicate signals passing through a longer path.
FIG. 3 reveals that the RAS control signal is transmitted from a path nearest to a RAS chain to a path farthest from the RAS chain. Also, final output data DQ is output at an instant of time when data RD is output from the longest path of a memory cell array block.
In FIG. 3, only skews in a word line WL and a bit line sense enable BLSE, in which output of data is delayed for a long time, are considered.
When the shortest path is selected, the final output data DQ is in fact output not in synchronization with a signal output from the shortest path, but in synchronization with a signal output from the longest path. A time difference between a signal output from the shortest path and a signal output from the longest path is due to skew and is about 1-2 nsec.
FIG. 4 is a diagram illustrating a structure of a conventional semiconductor memory device. The conventional semiconductor memory device of FIG. 4 includes a plurality of memory array blocks 21, a RAS chain 23, a CAS chain 24, and a plurality of multiplexers 25.
Each of the plurality of memory array blocks 21 includes a predetermined number of memory cells for storage of data. The RAS chain 23 is arranged at one side of the plurality of memory array blocks 21 in the row direction and outputs a RAS control signal for activating a word line of a memory cell.
The CAS chain 24 is arranged in the column direction at the bottom of the plurality of memory array blocks 21, and selects a bit line of a particular memory cell, amplifies data from the bit line, and outputs the amplified data.
The plurality of multiplexers 25 are connected to the plurality of memory array blocks 21, respectively. The plurality of multiplexers 25 pre-fetch 8-bit data from the plurality of memory array blocks 21 for speedy transmission of data. The pre-fetched data is converted into serial data DQ0 through DQ7 by the plurality of multiplexers 25.
The serial data DQ0 through DQ7 must be input or output in response to the same clock. Therefore, the data DQ7, which is first output from the memory array block 21, is in a stand-by mode until the data DQ0 is set up. The latency time of DQ7 depends on variations in factors such as the manufacturing temperature, process, and supplied voltage. Thus, the semiconductor memory device is designed such that the data DQ7 is output after a latency time that is longer than the skew.
Accordingly, a conventional semiconductor memory device is designed to receive or transmit data based on the longest path for data and has a reduced operating speed.
The present invention provides a semiconductor memory device with improved operating speed, in which data is input or output in synchronization with a signal input to or output from the shortest path.
According to one aspect of the present invention, there is provided a semiconductor memory device in which a plurality of memory cells are arranged in the form of a matrix in the row and column directions, the semiconductor memory device including a plurality of memory array blocks that each have predetermined numbers of memory cells and are arranged in the row direction; an RAS chain that is aligned at a first side of the plurality of memory array blocks in the row direction, and selects and activates a particular word line; a CAS chain that is aligned at the other side of the plurality of memory array blocks in the column direction and amplifies N bits of data from the plurality of memory array blocks and outputs the result to an input/output (IO) line (N is a natural number more than 2); and a data converter that continuously outputs the N bits of data input via the IO line from a memory array block nearest to the RAS chain to a memory array block farthest from the RAS chain.
According to another aspect of the present invention, there is also provided a semiconductor memory device in which a plurality of memory cells are arranged in the form of a matrix in the row and column directions, the semiconductor memory device including a plurality of memory array blocks that have predetermined numbers of memory cells and are arranged in the row direction; an RAS chain that is arranged at a first side of the plurality of memory array blocks in the row direction, and selects and activates a particular word line; a CAS chain that is arranged at the other side of the plurality of memory array blocks in the column direction, and amplifies N bits of data output from the plurality of memory array blocks and outputs the amplified N bits of data to an IO line, wherein N is a natural number more than 2; and a plurality of multiplexers that converts the N bits of data input via the IO line into serial data, and outputs the serial data. The respective memory array blocks are divided into predetermined numbers of memory sub-blocks, and the nearer a memory array block is to the RAS chain, the smaller the number of the memory sub-blocks of the memory array block.